1. Field of the Invention
The present invention relates in general to a system for testing circuits embedded in an integrated circuit (IC), and in particular to a system that may be flexibly partitioned between components internal and external to the IC.
2. Description of Related Art
Many integrated circuits (ICs) include one or more embedded circuits such as random access memories (RAMs). While logic circuits implemented in an IC itself may read or write access an embedded RAM, the bus conveying data, address and control signals between the RAM and the logic circuits read and write accessing it may not be accessible to external test equipment via the IC""s input/output (I/O) terminals. Conventional IC testers external to the IC therefore can""t directly test such an embedded RAM.
One way to allow an external IC tester to test an embedded RAM is to link the RAM""s I/O ports to the IC""s I/O terminals. However this approach requires a large number of extra I/O terminals to accommodate the RAM""s I/O ports and can require a substantial amount of scarce space within the IC to route large buses between each embedded RAM and the IC""s I/O terminals. Another way to allow provide a IC tester with access to terminals of an embedded RAM or other circuit is multiplex its terminals onto I/O terminals of other circuits so that an IC tester can selectively access the embedded circuit terminals as illustrated in FIG. 1. This approach can eliminate the need for extra I/O terminals, but can still require substantial amounts of IC space for routing the large embedded memory buses.
FIG. 2 illustrates a third approach to providing an IC tester with access to an embedded circuit. A xe2x80x9cbuilt-in self-testxe2x80x9d (BIST) circuit is formed on the IC that is designed to test the embedded circuit. A BIST circuit may require relatively few connections to the IC""s I/O terminals for communicating with external test circuits. Thus when the BIST circuit is located proximate to the RAM or RAMs it tests, signal routing paths between the BIST circuit and the I/O terminals can require less space on the IC than would be required if the RAMs"" I/O ports were directly routed to the IC""s I/O terminals. The number and nature of the connections between the BIST circuit and the IC""s I/O terminals depend on the nature of the test to be performed and on how test functions are apportioned between the IC""s internal BIST circuit and equipment external to the IC that communicates with the BIST circuit. For example a self-contained BIST circuit carrying out all aspects of a simple pass/fail test may require only a START signal input to initiate the test, a DONE signal output to indicate the test is complete, and a PASS/FAIL signal output to indicate the results of a test. When the BIST circuit requires an external controller providing timing signals for sequencing address and data generation, additional IC I/O ports are needed to supply those timing signals to the BIST circuit. Also more I/O terminal connections may be needed when the BIST circuit is to report the address of each defective memory cell to external test circuits.
When an IC includes more than one embedded RAM it is possible to use a single BIST circuit to test each RAM in turn, provided however that all RAMs are similar and are to be tested in the same manner. But this approach requires routing large buses within the IC for connecting a central BIST circuit to each embedded RAM, and those buses can require substantial space in the IC. It not possible to use a single BIST circuit for testing multiple embedded RAMs when the embedded RAMs have differing address ranges or are to be tested in different ways.
To the extent possible, an IC designer usually prefers to design the layout of an IC by defining interconnections between a set of xe2x80x9cstandard cellsxe2x80x9d, each standard cell specifying the layout within an IC of a component having a specific function. For example a standard cell might define the layout of an embedded memory, an I/O port, or any of many types of logic circuits. The designer""s job is simplified when it is not necessary for him to design any cells in detail or to substantially modify the design of any standard cell when incorporating it into an IC.
Since each RAM embedded in an IC may be of differing size and have differing test requirements, an IC designer will typically provide a separate customized BIST circuit for each embedded RAM. A number of other factors also influence the nature of a BIST design. For example the available space within an IC and the number of available I/O terminals can influence how we apportion test functions between a BIST circuit and external test circuits.
Since IC designers must custom design a test system for each IC to suit the nature of its embedded RAMs, they find BIST systems difficult to implement. What is needed is a system for testing RAMs embedded in an IC that allows a designer to flexibly apportion test functions between internal BIST circuits and external test circuits and which can test embedded RAMs of varying numbers and sizes in any of several ways, but which the designer can easily implement using standard cells requiring minimal modification.
A test system in accordance with the invention includes a built-in self-test (BIST) circuit incorporated into an integrated circuit (IC) for testing one or more random access memories (RAMs) of varying size embedded in the IC. During normal circuit operation logic circuits implemented within the IC read and write access the RAMs. During a RAM test, the BIST system disconnects the logic circuits from the RAMs and connects internal test circuits to the RAMs I/O ports to enable them to test the RAMs.
The BIST circuit is capable of operating in any of several modes when testing each embedded RAM, with its mode of operation being selected by a controller that may be conveniently implemented internal or external to the IC. Selectable modes include:
a RAM xe2x80x9cpass/failxe2x80x9d mode in which the BIST circuit tests each address of each RAM and generates an output FAILX signal indicating wherein any address of any RAM is defective;
a xe2x80x9cbit mapxe2x80x9d mode in which the BIST circuit tests each address of each RAM and produces output data indicating the pass/fail status of each bit at that RAM address, thereby providing a map of defective RAM storage bits;
a xe2x80x9cword mapxe2x80x9d mode in which the BIST circuit tests each RAM address and produces an output signal indicating whether that RAM address is defective, thereby providing a map of defective RAM addresses;
a xe2x80x9cscan capturexe2x80x9d mode in which the BIST circuit captures data appearing on each RAM""s bus in a scan register in response to a CAPTURE signal from the external control and serially shifts it out to the controller in response to a SHIFT signal from the controller; and
a xe2x80x9cscan forcexe2x80x9d mode in which the BIST circuit receives and stores data from the controller in the scan register and forces it onto the bus of an embedded RAM in response to a FORCE signal from the controller.
In accordance with another aspect of the invention, the BIST circuit includes a set of xe2x80x9ccore wrappersxe2x80x9d, each incorporated into the IC near a corresponding one of the embedded RAMs. Each core wrapper includes a test circuit that it connects to the bus of its corresponding RAM during a test. When connected to the bus of its corresponding RAM, each test circuit writes data into each RAM address within the RAM""s range of addresses, reads data out of each RAM address, and compares the data it reads out of each RAM address to the data it wrote into that RAM address to determine whether the RAM address is defective.
Each test circuit pulses an output error signal (CERR) whenever it determines a RAM address is defective, continuously asserts another output error signal (FAIL) after determining any RAM address is defective, and asserts a DONE signal when it has completed testing all RAM addresses. A glue logic circuit included in the IC logically ANDs the DONE output signals of the test circuits of all core wrappers to produce a single output DONEX signal, logically ORs the FAIL output signals of the test circuits of all core wrappers to produce a single output FAILX signal and multiplexes the CERR output signal of the test circuits of all core wrappers to select one of the them as a single output CERRX signal in response to selection data from an external controller. The controller monitors the DONE signal to determine when the test is complete during all modes of operation, monitors the FAILX signal during the pass/fail mode of operation to determine whether any IC is defective, and selects and monitors the glue logic output CERRX signal during the word map mode of operation to determine which memory addresses are defective.
In accordance with another aspect of the invention the controller sends each the test circuits within each core wrapper MIN, MAX data defining the range of addresses of the corresponding RAM. When it tests the RAM in any mode of operation, each test circuit restricts its test activities to that range of addresses.
In accordance with another aspect of the invention, the controller sends ROW/COL data to the test circuit of each core wrapper controlling whether the test circuit accesses RAM addresses on a row-by-row or column-by-column basis in any mode of operation.
In accordance with another aspect of the invention, each core wrapper includes a scan register for storing data appearing on the bus of the corresponding RAM in response to an input CAPTURE signal and for shifting that data out to a test circuit external to the IC in response to an input SHIFT signal when operating in the scan capture mode.
In accordance with another aspect of the invention, the test circuit within each core wrapper generates RESULTS data after testing each address of the corresponding RAM, when operating in the bit map mode. The results data indicates whether each bit of data written into that RAM address matches a corresponding bit of data read back out of that RAM address. The RESULTS data provides an additional input to the scan register so that may be stored in the scan register in response to the CAPTURE signal and shifted out to the controller in response to the SHIFT signal.
The controller provides DIAG input data to the test circuit within each core wrapper controlling whether it is to operate in the bit map mode. When operating in the other modes a tester tests each successive RAM address without waiting for the external control to capture and acquire RESULTS data. In the bit map mode, each tester waits for a READY signal from a controller after testing each RAM address before testing a next RAM address. The wait allows the controller time to capture and acquire the RESULTS data stored in the scan register.
In accordance with a further aspect of the invention, the function of the controller may be flexibly partitioned between a controller implemented internal to the IC, a controller implemented outside the IC, and a conventional general purpose integrated circuit tester without modifying the nature of the core wrappers or the glue logic circuit.
It is accordingly an object of the invention to provide a system for testing one or more RAMs of varying size embedded in an IC.
It is another object of the invention to provide a test system allowing an IC designer to flexibly select a manner in which each RAM is tested and to flexibly apportion test functions between test circuits internal and external to the IC.
It is a further object of the invention to provide an embedded memory test system that may be easily incorporated into an IC using standard cells requiring minimal customization, regardless of the size and number of embedded RAMs and regardless of the nature of the test or tests to be performed on each embedded RAM.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.